The performance of a semiconductor integrated circuit, such as a large scale integrated circuit (LSI), largely depends on its operational timings, which are based on the cycle time (i.e., the inverse of the operational frequency). When designing an integrated circuit, the circuit is designed such that the delay values, racing values, and other operational timing indices fall within design target values for all paths on the circuit. In other words, the circuit is designed such that its operational frequency is at least a design target value. Methods for increasing the operational frequency of paths may include logic modifications, layout improvements, and suppression of line resistance, for example, as well as increasing the drivability of cells. The “operational frequency” referred to herein is the upper limit value of the clock frequency of the circuit at which operation is possible. In addition, the “cycle time” refers to the period of one clock cycle at the limit frequency of the circuit at which operation is possible. The cycle time is computed by taking the inverse of the upper limit operational frequency. Furthermore, the “operational timing” refers to the delay values, racing values, and other design indices that all paths on the circuit should meet within the target operational frequency.
There exists technology for optimizing the drivability of cells for set paths, and achieving a target operational frequency.
In addition, there exists statistical static timing analysis (SSTA), wherein delays occurring in individual cells on a path are treated as probability distributions, and the operational frequencies of paths are statistically analyzed.
However, if the drivability of cells is raised by increasing the cell size, power consumption of the cells also increases. In other words, there is a trade-off between power consumption, and the operational frequency or the cycle time (i.e., the inverse of the operational frequency).
When optimizing a circuit such that the operational frequencies of individual paths achieve a target operational frequency, the cycle times of individual paths become concentrated near the cycle time corresponding to the target operational frequency. For the subset of paths on the circuit that do not achieve the target cycle time (i.e., the inverse of the target operational frequency), the drivability of cells is raised until the target cycle time for the subset of paths is achieved. Meanwhile, for the paths that do satisfy the target cycle time, the cell size might be further increased to obtain a delay margin. However, such paths are not replaced with larger cells having higher drivability in such cases, due to considerations from the perspective of power consumption and chip size.
Some cells may have input terminals connected to the output terminals of a plurality of cells. Such cells are used on a plurality of paths, and are thus shared by a plurality of paths. For such a cell, the actual delay produced during cell operation may increase beyond the maximum static delay between that cell's input terminals and output terminals. For this reason, in cases where there are many paths near the target operational frequency (i.e., in cases where there are many paths with small margins with respect to the target cycle time), there is a possibility that an actually fabricated semiconductor integrated circuit with such paths may not operate at the target operational frequency, due to the effects of delays in cells shared by a plurality of paths.
With semiconductor integrated circuits, a plurality of circuits is simultaneously formed on a silicon wafer. In some cases, however, irregularities in fabrication precision may occur, depending on the position of the circuits on the silicon wafer. For this reason, depending on the position of the circuits on the silicon wafer, there might be produced circuits that do achieve the target operational frequency, as well as circuits that do not achieve the target operational frequency, even when fabricating semiconductor integrated circuits with the same design. Such fabrication irregularities increase with increases in the number of paths with small margins in operational frequency. For this reason, when there are many paths with small margins, the timing yield (i.e., frequency yield) drops.
When optimizing cell sizes and cell drivability for power consumption and delay margins in this way, there is demand to optimize by replacing cells with larger cells having higher drivability, but without producing paths where the operational frequency or the cycle time drops.
Thus, the realization of technology to support such optimization is an important issue. Such technology needs to support the optimization of cell size or cell drivability without affecting the operational frequency or the cycle time of the circuit as a whole.
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